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Vol: 56(70) No: 3 / September 2011

An Approach for Generating Synthesizable VHDL Code from Data Flow Graphs
Philip I. Necsulescu
School of Information Technology and Engineering (SITE), University of Ottawa, Faculty of Graduate and Post Doctoral Studies, Ottawa, Canada, e-mail: necsup@gmail.com
Voicu Groza
School of Information Technology and Engineering (SITE), University of Ottawa, Faculty of Engineering, Ottawa, Canada, e-mail: groza@site.uottawa.ca


Keywords: FPGA, Custom Instruction, Automatic Generation of VHDL code, Hardware Development, Data Flow Graph, Instruction Set Extension

Abstract
The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. In this article, the methodology used by SHIRA for the module used to generate syntheizable VHDL code from a Data Flow Graph (DFG) when it is used as the Intermediate Representation (IR) is described. The implementation of this approach is writen in Java, making use of Object Oriented Programming (OOP) principles. The SHIRA hardware generation module uses the DFG generated by the SHIRA toolchiain which itself is derived from a standard C program. The methodolgy is described for two cases: employing a separate component for each node in the DFG and when employing component reuses, that is allowing components to be used by multiple graph nodes. The two cases are then tested with some simple C programs on a standard Altera FPGA using a NIOS II/e processor with the generated VHDL code being added to the NIOS II/e instruction set as a Custom Instruction (CI). The results are then compared with the generic case of using only the standard processor instruction set, for the case when using a separate hardware component for each node in the DFG, and for the case allowing component reuse.

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