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Vol: 47(61) No: 1 / March 2002 AES Implementation Using VHDL David Lazar Technical University of Cluj-Napoca, Faculty of Automation and Computers, Department of Computer Science, 24-26 Bariţiu street, 3400, Cluj-Napoca, Romania, phone: (0264)-194834, e-mail: david@c7.campus.utcluj.ro Horea Haitonic Technical University of Cluj-Napoca, Faculty of Automation and Computers, Department of Computer Science, 24-26 Baritiu street, 3400, Cluj-Napoca, Romania, e-mail: horeah@personal.ro Octavian Cret Technical University of Cluj-Napoca, Faculty of Automation and Computers, Department of Computer Science, 24-26 Baritiu street, 3400, Cluj-Napoca, Romania, e-mail: Octavian.Cret@cs.utcluj.ro Keywords: AES, Rijndael algorithm, encryption, VHDL Abstract In this paper we describe a hardware implementation of the AES (Advanced Encryption Standard) algorithm. After a brief introduction to AES concepts, the modules that accomplish the encryption, respectively the decryption, are presented. The implementation was realized using the VHDL hardware description language and the simulation was performed using the Active-HDL environment. References [1] National Institute of Standards and Technology, (2001), Federal Information Processing Standards Publication 197 http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf [2] J. Daemen and V. Rijmen, (1999), AES proposal: Rijndael, AES Algorithm Submission http://www.esat.kuleuven.ac.be/~rijmen/rijndael/ |