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Vol: 57(71) No: 4 / December 2012 

Effect of Layer Thicknesses on the Memory Hysteresis of MNOS Structures – Results of Computer Simulations
K. Z. Molnár
Institute of Microelectronics and Technology, Óbuda University, Kandó Kálmán Faculty of Electrical Engineering, Tavaszmező u. 15-17, H-1084 Budapest, Hungary, phone: (361) 6665054, e-mail: Molnar.Karoly@kvk.uni-obuda.hu
Zs. J. Horváth
Hungarian Academy of Sciences, Research Centre for Natural Sciences, Institute for Technical Physics and Materials Science, Konkoly Thege Miklós u. 29-33, H-1121 Budapest, Hungary, phone: (361) 6665145, e-mail: horvzsj@mfa.kfki.hu


Keywords: computer simulation, silicon nitride, MNOS, non-volatile memory, tunneling current, memory hsyteresis

Abstract
Electron and hole tunneling probability is calculated and memory hysteresis behaviour of MNOS structures are simulated by integrating the difference of the current via the oxide and nitride layer. The effect of the oxide and nitride thickness as well as the depth of charge centroid is studied. The results indicate that the optimal oxide thickness is about 2 nm. A thin nitride layer decreases the efficiency of the injected charge. It has been obtained that the possible highest memory window width decreases monotonically with increasing depth of charge centroid.

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